发明名称 |
Programmable high speed quiet I/O cell |
摘要 |
An output buffer circuit includes multiple programmable boost drive stages which allow selection of one of several drive strengths to accommodate a range of output load conditions, thereby achieving low noise and low power dissipation. In one embodiment, one or more of the boost circuits turn on after the primary driver circuit is turned on, and turn off before the primary circuit is turned off, thereby achieving soft turn-on and turn-off.
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申请公布号 |
US6281706(B1) |
申请公布日期 |
2001.08.28 |
申请号 |
US19980052042 |
申请日期 |
1998.03.30 |
申请人 |
NATIONAL SEMICONDUCTOR CORP. |
发明人 |
WERT JOSEPH D.;DAUGHERTY DAN E.;DUNCAN RICHARD L. |
分类号 |
H03K19/00;H03K19/003;(IPC1-7):H03K19/017 |
主分类号 |
H03K19/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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