| 摘要 |
PCT No. PCT/SE96/00010 Sec. 371 Date Aug. 1, 1997 Sec. 102(e) Date Aug. 1, 1997 PCT Filed Jan. 10, 1996 PCT Pub. No. WO96/21897 PCT Pub. Date Jul. 18, 1996A data transmission system, in which data streams shall be transmitted with great speed between a sending clock domain and a receiving clock domain, which operate with mutually different clock speeds, includes two system part circuits. One of these system part circuits is designed to receive from the first clock domain a data stream with the clock speed of the first clock domain and, controlled by this clock speed, serial/parallel convert the data stream to parallel data streams, each with a clock speed that is a certain fraction of the clock speed of the first clock domain. The other system part circuit is designed to receive the parallel data streams and, controlled by the clock speed of the other clock domain, parallel/serial convert them to an output data stream, which with the clock speed of the second clock domain is sent to the second clock domain. |
