发明名称 MULTIPLIER
摘要 PURPOSE: A multiplier is provided to construct gates consisting of pass transistors without standard gates, and to perform shifting and adding operations without clocks so that it can reduce the number of transistors by 50% and the operation time. CONSTITUTION: The circuit comprises the first shifter(11), 7 bit adders(12,13), and an 8 bit adder(14). The first shifter(11) shifts a 4 bit multiplicand by 0 bit to 3 bit according to each bit value of a 4 bit multiplier. The 7 bit adder(12) adds Ma and Mb among the 4 shifted multiplicands(Ma-Md) and outputs the added result(Mab). The 7 bit adder(13) adds Mc and Md among the 4 shifted multiplicands(Ma-Md) and outputs the added result(Mcd). The 8 bit adder(14) adds the added results(Mab, Mcd) of the 7 bit adders(12,13). The first shifter(11) includes pass transistors for shifting a multiplier to a left by 0 to 3 bit according to each bit value of a multiplicand. The 7 bit adder(12) includes the second shifter, a select signal generator, an operation output module, and a carry generator. The other 7 bit adder(13) has the same circuit as the 7 bit adder(12). The 8 bit adder(14) is simply constructed by adding an XOR gate, an AND gate, a transistor of the second shifter, a select signal generator and an operation output module to the circuit of the 7 bit adder(12).
申请公布号 KR100308124(B1) 申请公布日期 2001.08.27
申请号 KR19980008784 申请日期 1998.03.16
申请人 HYUNDAI MICRO ELECTRONICS CO., LTD. 发明人 CHOI, GWANG GYU
分类号 G06F7/52;(IPC1-7):G06F7/52 主分类号 G06F7/52
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