| 摘要 |
A methodology and circuit modeling structure for analyzing the packaging of electrical circuits and determining electrical circuit properties, e.g., inductance, capacitance, of circuits and circuit structures found in VLSI chips, PC cards, boards, microwave circuits, etc. The methodology and circuit modeling structure includes modifying the original signal line structure in the circuit to be analyzed by including a shadow line structure in the analyzed circuit and locating the shadow line structure between a ground plane structure and an associated signal line structure at an infinitesimal distance above the ground plane. Additionally, for each shadow line structure, there is provided a first via structure for connecting a first end of said shadow line to the ground plane and, a second via structure connecting a second end of the shadow line to the ground plane. The modified shadow line structure is readily implemented in 3D circuit package analysis programs and provides a computationally efficient way to analyze complex types electrical/electronic/packaging circuits and structures.
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