| 摘要 |
PROBLEM TO BE SOLVED: To reduce the number of wirings and the area of a gain cell as well. SOLUTION: A memory cell MC has a write transistor TW and read transistor TR inside, and the read transistor TR is e.g. a thin film transistor having a gate connected to a read word line RWL, a source and a drain either of which is connected to a bit line BL and the other connected to a power line VDD. The write transistor TW has a gate connected to a write word line WWL, a source and a drain either of which is connected to the bit line BL and the other capacitively coupled with an active layer of the read transistor TR and the write transistor TW may be an SOI type transistor. |
