| 摘要 |
<p>PROBLEM TO BE SOLVED: To provide a clock driver circuit of reduced clock skewness and a clock wiring method by adjusting the length of adjacent wirings and the ununiformity of a wiring capacity due to crossing of intercalation wiring. SOLUTION: The clock driver circuit consists of an input terminal 100 to which a single-phase clock signal is inputted, a first stage clock driver circuit 101 connected to this input terminal for converting the single-phase clock signal to normal phase and anti-phase clock signals to output it, intermediate clock driver circuits 102 to 10N for repeating the normal phase and anti-phase clock signals outputted from this driver 101, final stage clock driver circuits 201 to 20N for converting the normal phase and anti-phase clock signals repeated by these circuits 102 to 10n a single-phase clock signal and outputting it and two wirings 11 to 1N connecting the circuits 201 to 20N through the circuits 102 to 10N from the driver circuit 101 to transmit the normal phase and anti- phase clock signals. The two wirings 11 to 1N are arranged as adjacently as possible.</p> |
