| 摘要 |
PROBLEM TO BE SOLVED: To correctly receive digital transmission data even when a phase shift takes place in a sampling clock in the case of receiving the digital transmission data. SOLUTION: Delay circuits 203, 204, 206 sequentially delay received data 201. The received data 201 and delayed data signals 203, 205, 207 are sampled at a leading edge and a trailing edge of a clock with the same frequency as a data transfer rate. In the case that N-sets of consecutive samples of the received data 201 are the same value V (V=1 or 0), it is discriminated that (N/2) sets of data with the value V are continuously received when the N is an even number. When the N is an odd number, an even number (M) of consecutive samples with the same value V is selected from samples of the delayed data signals 203, 205, 107 and it is discriminated that (M/2) sets of data with the value V are continuously received.
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