发明名称 HIERARCHICAL LAYOUT DESIGNING TECHNIQUE
摘要 PROBLEM TO BE SOLVED: To provide a hierarchical layout designing technique for integrated circuits which can ensure desired specifications and apply to many types of circuits flexibly at a high efficiency. SOLUTION: Such a structure is provided that the size is changeable while extending wirings 102 in hard macros in the horizontal and vertical directions within a range within which specifications are held, and buffer blocks 103 for wirings passing on the hard macros and wirings 104 passing on the hard macros can be laid between divided hard macros 101. The hard macros may be divided into a plurality of divisions in either horizontal or vertical direction, and the buffer blocks 103 for wirings passing on the hard macros are laid in the same direction as the wirings passing on the hard macros.
申请公布号 JP2001230327(A) 申请公布日期 2001.08.24
申请号 JP20000040023 申请日期 2000.02.17
申请人 NEC MICROSYSTEMS LTD 发明人 DOCHI KUNIYUKI
分类号 H01L21/82;G06F17/50;(IPC1-7):H01L21/82 主分类号 H01L21/82
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