发明名称 BUS INTERFACE CONTROLLER
摘要 PROBLEM TO BE SOLVED: To apply a Utopia Level 12 bus interface to a device like a package of PHY layer devices by making it possible to accurately detect a cell-available signal even when an ATM layer device is not mounted in a device package. SOLUTION: A cell-available signal on a bus which was held by the unmounted state of a device package and the capacity component of a bus is eliminated by controlling the output of an output buffer 110 with a control signal so that after the cell available signal '1' of a PHY layer device is outputted for a 1-clock cycle period, an output control circuit 5 further outputs a 1/2-clock-cycle period '0'.
申请公布号 JP2001229121(A) 申请公布日期 2001.08.24
申请号 JP20000040824 申请日期 2000.02.18
申请人 MITSUBISHI ELECTRIC CORP 发明人 ASASHIBA NORIHIRO;AKITA MINORU
分类号 G06F13/366;H04L12/28;(IPC1-7):G06F13/366 主分类号 G06F13/366
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