| 摘要 |
PROBLEM TO BE SOLVED: To provide a clock signal extraction circuit which can stably conduct phase correction without using a high speed device with less clock distortion. SOLUTION: When received data whose phase is delayed compared to an extraction clock C2 is inputted in a state where a 1/8 delay clock signal is selected and outputted as an extracted clock C2, an up/down counter 2 up-counts the output of an edge detection circuit 52. An eight channel selector 3 selects and outputs a 2/8 delay clock signal L2 delayed by 1/8 of a clock period. When the phase of next received data is also delayed, up-counting is conducted again, and the eight channel selector 3 selects and outputs a 3/8 delay clock signal L3 delayed by 1/8 of the clock period. The phase in similarly corrected afterward and received data and the extracted clock become ideal in phase. |
