| 摘要 |
PROBLEM TO BE SOLVED: To provide a turbo decoder, which further reduces power consumption, while suppressing the delay of processing speed. SOLUTION: The data position of low reliability in the soft decided result of a repeating process, outputted from a repeated decoding part composed of SISO decoders 1-1 and 1-2, interleavers 2-1 and 2-2 and a deinterleaver 3 is preserved in a low reliability data position preserving part 4, the logic of data at the data position preserved in the low reliability data position preserving part 4 is inverted by a bit inverter circuit 7-3, CRC checks are performed simultaneously by CRC check circuits 7-11. 7-12,..., 7-1m and 7-1n. When the absence of error in the CRC checked result is decided, the repetition of the decoding process is finished by a repetition control circuit 7-4 and the decoded result is outputted by a selector circuit 7-2.
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