发明名称 METHOD FOR FABRICATING SEMICONDUCTOR ELEMENT FOR PREVENTING ELECTRICAL SHORT CIRCUIT OF UPPER LAYER INTERCONNECTION AND LOWER LAYER INTERCONNECTION BASED ON FLUIDITY OF PLANALIZATION FILM
摘要 PROBLEM TO BE SOLVED: To prevent a lower layer inter connection formed on a BPSG film from being short-circuited electrically with an upper layer interconnection formed subsequently due to flow of the BPSG film occurring during a thermal process. SOLUTION: The method for fabricating a semiconductor device comprises a step for forming a transistor on a semiconductor substrate 21, a step for depositing a first interlayer insulation film 28 on the semiconductor substrate to cover the transistor, a step for depositing a BPSG film 29 as a planalization film on the first interlayer insulation film, a step for flowing the BPSG film, a step for etching the surface of the BPSG film by sputtering utilizing Ar ions such that the first interlayer insulation film including the BPSG film is exposed while being planalized, a step for forming an interconnection 30 on the exposed first interlayer insulation film, a step for depositing a second interlayer insulation film 31 on the first interlayer insulation film and the BPSG film to cover the interconnection, and a step for forming a metal electrode 33 containing with a specified part of the transistor on the second interlayer insulation film.
申请公布号 JP2001230319(A) 申请公布日期 2001.08.24
申请号 JP20000391349 申请日期 2000.12.22
申请人 HYNIX SEMICONDUCTOR INC 发明人 RI SEIKEN
分类号 H01L21/302;H01L21/3065;H01L21/316;H01L21/768;H01L27/10;(IPC1-7):H01L21/768;H01L21/306 主分类号 H01L21/302
代理机构 代理人
主权项
地址