| 摘要 |
PROBLEM TO BE SOLVED: To reduce the layout area of a memory cell array. SOLUTION: Well regions 11 and well isolating regions 12 are made in parallel with each other and besides alternately, and the first active regions 17S to serve as source regions and the second active regions 17D to serve as drain regions are made alternately on the surface of the wall regions 11. A source line 15 is connected to the first active region 17S, and a bit line 14 is connected to the second active region 17D. A gate electrode is made through a gate insulating film consisting of a ferroelectric film is made between the first active region 17S and the second active region 17D on the well region 11, and a word line 13 is connected to that gate electrode. First, second, third, and fourth MFSFETs 16A, 16B, 16C, and 16D are made severally in the region which becomes the intersecting point between the word line 13 and the well region 11. The first to fourth MFSFETs 16A-16D which own the same well region 11 in common and adjoin one another own the first active region 17S or the second active region 17D.
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