发明名称 Fet bias circuit
摘要 A circuit for biasing an FET, comparing a gate bias voltage of the FET with a reference voltage at an operational amplifier and performing closed-loop control on the gate bias voltage of the FET with the output of the operational amplifier. The temperature characteristics of the mutual conductance of the FET is compensated by setting the temperature characteristics of one or both of two voltage dividing resistors. Variations in a drain bias current due to input signal level and temperature changes can be suppressed. The circuit at the gate and the circuit at the drain are separate, making possible class A, class AB, and class B operations. The voltage drop at the gate resistor can be ignored so that the gate resistor can be designed with priority given to stability of the RF characteristics.
申请公布号 US2001015668(A1) 申请公布日期 2001.08.23
申请号 US20010773354 申请日期 2001.01.31
申请人 SAKAMOTO HIRONORI;HONDA TAMAKI;TAKAHASHI TAKETO 发明人 SAKAMOTO HIRONORI;HONDA TAMAKI;TAKAHASHI TAKETO
分类号 H03F1/30;H03F3/193;(IPC1-7):H03L5/00 主分类号 H03F1/30
代理机构 代理人
主权项
地址