发明名称 Electron beam drawing process and electron beam drawing apparatus
摘要 An electron beam drawing process of high throughput, coping with the changes in static distortion and dynamic distortion of a lower layer exposure apparatus or an optical reduction exposure apparatus. At least two marks formed in each chip formed on a wafer are detected for a predetermined number of chips, and the relation between the shape distortion of each chip in the wafer plane and the wafer coordinates is determined from the positions of the detected marks and the designed positions of the marks by a statistical processing. Patterns are drawn in all chips while correcting the patterns to be drawn on the individual chips, by using the relation between the determined chip shape distortion and the wafer coordinates. As a result, the superposition exposure with the lower layer can be achieved with a high throughput and with a high accuracy without any manual adjustment.
申请公布号 US2001015413(A1) 申请公布日期 2001.08.23
申请号 US20010843786 申请日期 2001.04.30
申请人 HITACHI, LTD. 发明人 SASAKI MINORU;TANGE YUJI;HOJYO YUTAKA;OONUKI KAZUYOSHI;ITOH HIROYUKI
分类号 G03F7/20;H01J37/304;H01J37/317;(IPC1-7):G21G5/00;A61N5/00 主分类号 G03F7/20
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