| 摘要 |
A multiplier circuit has an encoder and a partial product bit generating circuit. The encoder receives a multiplier bit signal and is used to output a plurality of encode signals. The partial product bit generating circuit receives the encode signals along with a multiplicand bit signal from each digit place and is used to generate a partial product bit for each digit place. The partial product bit generating circuit has a first selection circuit which is used to select a logically true signal from among the encode signals in accordance with a value of the multiplicand bit signal. Therefore, the circuit can be reduced in size by reducing the number of necessary elements without sacrificing its high speed capability.
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