| 摘要 |
A sync frequency conversion circuit comprises first circuits for forming a write control signal changeable in synchronism with horizontal and vertical sync frequencies of an input video signal; a memory where the input video signal is written by the write control signal; a discriminator for discriminating the horizontal and vertical sync frequencies of the input video signal; a phase locked loop controlled by the discrimination result obtained from the discriminator, and serving to output a clock signal of a frequency changeable in accordance with such discrimination result; and second circuits for forming a read control signal from both of the discrimination output of the discriminator and the clock signal. The read control signal is supplied to the memory so that the video signal written in the memory is read out therefrom in such a manner that the horizontal sync frequency, the horizontal blanking interval and the vertical blanking interval are maintained substantially at fixed values regardless of the horizontal sync frequency of the input video signal.
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