发明名称 |
Method for analyzing circuit pattern defects and a system thereof |
摘要 |
In order to allow critical flaws in an inspected item to be known early during a production process, the present invention includes the following steps: a step for detecting defects in a production process for the inspected item and storing defect positions; a step for collecting detailed defect information and storing the detailed information in association with defect positions; a step for storing positions at which flaws were generated based on a final inspection of the inspected item; a step for comparing defect positions with positions at which flaws were generated; and a step for classifying and displaying information based on the comparison results.
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申请公布号 |
US2001016061(A1) |
申请公布日期 |
2001.08.23 |
申请号 |
US20010783604 |
申请日期 |
2001.02.15 |
申请人 |
SHIMODA ATSUSHI;ISHIMARU ICHIROU;TAKAGI YUJI;TAMURA TAKUO;HAMAMURA YUICHI;WATANABE KENJI;OZAWA YASUHIKO;ISOGAI SEIJI |
发明人 |
SHIMODA ATSUSHI;ISHIMARU ICHIROU;TAKAGI YUJI;TAMURA TAKUO;HAMAMURA YUICHI;WATANABE KENJI;OZAWA YASUHIKO;ISOGAI SEIJI |
分类号 |
G01N21/88;G01N21/94;G06T7/00;H01L21/66;(IPC1-7):G06K9/00 |
主分类号 |
G01N21/88 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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