| 摘要 |
A domino logic circuit includes input connections to receive a clock signal and an input data signal. In one embodiment, the domino logic circuit includes a dynamic stage comprising at least one n-channel pull-up transistor having a gate coupled to receive the input data signal. The n-channel pull-up transistor has a low threshold voltage. The dynamic stage can include an n-channel pull-down transistor which has a gate connection coupled to receive the clock signal. First and second inverter circuits can also be provided to latch a voltage on a drain of the pull-down transistor. Static logic circuits coupled to the dynamic stage have skewed rise and fall times to increase the propagation time of the domino circuit.
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