| 摘要 |
<p>A semiconductor memory device characterized by: a memory cell array including a plurality of memory cells arranged in rows and columns, said memory cell array comprising a first group array and a second group array each including a plurality of memory cell blocks, each of said memory cell blocks including a plurality of memory cells and at least one bit line to which said plurality of memory cells are connected, each of said memory cell blocks in said second group array having a corresponding memory cell block in said first group array, so that said memory cell block in said first group array and said memory cell block in said second group array and corresponding to each other form an adjoint pair; first addressing means supplied with address data for selecting a memory cell block in said first group array in response thereto, said first addressing means further selecting a bit line in said selected memory cell block; second addressing means supplied with said address data for selecting a memory cell block in said second group array in response thereto, said second addressing means further selecting a bit line in said selected memory cell block; selection control means supplied with said address data for controlling said first addressing means and said second addressing means for prohibiting the selection of a memory cell block in said first group array and a memory cell block in said second group array that form an adjoint pair; said memory cell blocks that form an adjoint pair having respective input/output lines for writing and/or reading information to and from a selected memory cell transistor that are connected commonly to a common input/output line, said common input/output line being provided in number corresponding to the number of said adjoint pairs; and switching means connected on the one hand with said plurality of input/output lines and on the other hand with input/output means for writing and/or reading information to and from a selected memory cell transistor, said switching means being controlled by said selection control means and connecting one of said input/output lines to said input/output means selectively in response to said address data.</p> |
