发明名称 |
Packet flow control apparatuses and methods for controlling the same |
摘要 |
<p>A packet flow control apparatus performing flow control of packets each having variable length, includes: a buffer memory (1) for temporarily accumulating arrived packets until a sending time of each packet; a counter updated based on a rate determined in accordance with a packet length calculated by a counter value of the counter and limited flow of packets; a sending time determining section (2) for determining the sending time of each packet based on the counter value and a present time; and a sending order control section (3) for managing a sending order of each packet accumulated in the buffer memory, and for sending a read instruction of each packet to the buffer memory, based on the sending time determined by the sending time determining section. <IMAGE></p> |
申请公布号 |
EP1126666(A2) |
申请公布日期 |
2001.08.22 |
申请号 |
EP20010102739 |
申请日期 |
2001.02.07 |
申请人 |
FUJITSU LIMITED |
发明人 |
KAWASAKI, TAKESHI;SOUMIYA, TOSHIO;NAKAMICHI, KOJI |
分类号 |
H04L12/56;(IPC1-7):H04L12/56 |
主分类号 |
H04L12/56 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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