| 摘要 |
A memory counter circuit, comprising a plurality of mutually connected counter stages (1a, 1), comprising: an internal address bus (2) which is interfaced with each one of the counter stages (1a, 1) and is adapted to send an external address signal (18) to each one of the counter stages; means (19, 20) for loading the external address signal (18) onto the internal address bus (2); means (3) for enabling the connection between the internal bus (2) and each one of the counter stages (1a, 1), the means being driven by a true address latch enable signal (ALE); means (15) for generating the true address latch enable signal (ALE) starting from an external address latch signal (16) and a fast address latch enable signal (ALE-fast) which is adapted to drive the means (19, 20) for loading the external address (18) onto the internal address bus (2); and means (21) for generating clock signals (M-inc, S-inc) for synchronizing each one of the counter stages (1a, 1), the synchronization signals not being simultaneously active. <IMAGE> |
