Circuit and method for determining the phase difference between a sample clock and a sampled signal

摘要

A circuit includes a buffer (42) for receiving and storing two samples of a signal, and a phase calculation circuit (46) for calculating a phase difference between one of the samples and a predetermined point of the signal. Such a circuit can be used to decrease the alignment-acquisition time of a digital timing-recovery loop, and allows a shortening of the sector preambles and a corresponding increase in the data-storage density of a disk. The circuit may determine an initial phase difference between a disk-drive read signal and a read-signal sample clock. The digital timing-recovery loop uses this phase difference to provide an initial coarse alignment between the read signal and the sample clock. By providing such coarse alignment, the recovery loop reduces the overall alignment-acquisition time. <IMAGE>