| 摘要 |
<p>A plurality of delay circuits (102, 104, 106) successively delay a received data (101). The received data (101) and delayed data signals (103, 105, 107) are sampled in response to both leading and trailing edges of a clock (109) having a frequency substantially identical with that of a data transmission rate of the received data. When a sampling value having the same value V (V=1 or 0) appears continuously N times in the sampling operation of the received data 101 (where N is an even number), it is judged that a data of value V is continuously received (N/2) times. <IMAGE></p> |
