Flash-erasable semiconductor memory device

摘要

A flash-erasable semiconductor memory device comprising: a memory cell array including a plurality of memory cell transistors, each of said memory cell transistors comprising: an insulated floating gate provided on a semiconductor substrate with a separation therefrom for storing information in the form of electric charges; a gate insulation film provided on an upper major surface of said semiconductor substrate for separating said floating gate from said semiconductor substrate; a channel region defined in said semiconductor substrate in correspondence to said floating gate electrode; a source region and a drain region defined in said semiconductor substrate at both sides of said floating gate, said source region injecting carriers into said channel region such that said carriers are transported along said channel region while said drain region collecting carriers that have been injected into said channel region at said source region and transported through said channel region, and a control electrode provided on said floating gate with a separation therefrom by said capacitor insulation film for controlling an injection of carriers from said channel region to said floating gate via said gate insulation film; addressing means supplied with address data for selecting a memory cell transistor in said memory cell array; writing means for writing information into said selected memory cell transistor; reading means for reading information from said selected memory cell transistor; and erasing means for erasing information from a plurality of memory cell transistors included in said memory cell array simultaneously, said erasing means erasing information by removing electric charges from said floating gate electrodes of said memory cell transistors by causing to flow a tunneling current through said gate insulation film; said memory cell array comprising a first memory cell array that includes a plurality of bit lines and a second memory cell array that includes also a plurality of bit lines, said source region of said plurality of memory cell transistors in said first and second memory cell arrays being connected, when erasing information, commonly to said erasing means for simultaneous erasing; said addressing means comprising a first addressing unit supplied with said address data for selecting a bit line in said first memory cell array and a second addressing unit supplied with said address data for selecting a bit line in said second memory cell array; address control means supplied with said address data for enabling one of said first and second addressing units while disabling the other of said first and second addressing units in response to said address data; and overriding means supplied with a control signal for selectively enabling one of said first and second addressing units in response to a first state of said control signal and for selectively enabling the other of said first and second addressing units in response to a second state of said control signal. <IMAGE>