Method for reducing branch target storage by calculating direct branch targets on the fly

摘要

A method for efficiently storing and determining predicted next fetch addresses is disclosed. Predicted fetch addresses are generated by a number of independent sources. Predicted fetch addresses for indirect branch instructions are stored in a indirect branch target cache. Predicted fetch addresses for direct branch instructions are calculated using an "on-the-fly" direct branch adder. Predicted fetch addresses for return instructions are stored in a return stack. Predicted fetch addresses for sequential instructions are calculated on-the-fly using a sequential address adder. A branch selector array is used to store selector bits that indicate which of the above sources should be selected for the next predicted fetch address. The selector bits each correspond to particular instruction bytes stored in an instruction cache. Predecode bits indicative of branch instructions and instruction boundaries may also be stored in the instruction cache. A microprocessor and computer system employing this method are also disclosed.