发明名称 |
Isolated well transistor structure for mitigation of single event upsets |
摘要 |
CMOS circuits are made resistant to erroneous signals produced by the impact of high energy charged particles (commonly known in the literature as Single Event Upset or SEU) by the addition of upset immune transistor structures into the circuits in such a way that they block and dissipate the erroneous signal. The added transistor structures are made immune to SEU by placing them in well diffusions that are separate from the rest of the circuit and biasing those wells such that the electric fields surrounding the transistors are very low in comparison to the rest of the circuit. Signal blocking is achieved with an SEU immune transistor that is in an "off" state whenever other circuit transistors that deliver signals through it are potentially sensitive to SEU. Dissipation is achieved with either a resistor or low current drive transistor that spreads the SEU signal out over time thereby reducing its voltage change to an acceptable level.
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申请公布号 |
US6278287(B1) |
申请公布日期 |
2001.08.21 |
申请号 |
US19990428239 |
申请日期 |
1999.10.27 |
申请人 |
THE BOEING COMPANY |
发明人 |
BAZE MARK P. |
分类号 |
G11C11/412;H01L21/761;H01L27/092;H03K19/003;(IPC1-7):H03K19/003;G11C11/34;H01L29/76 |
主分类号 |
G11C11/412 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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