Method and apparatus for 50% duty-cycle programmable divided-down clock with even and odd divisor rates

摘要

A 50% duty-cycle divided-down clock with selectable divisor rates. A simple architecture comprised of two n-bit counters, a state machine, 2 toggle flip-flops, and two 2-to-1 muxes is used to allow an input clock signal to be divided down by any divisor rate up to 2n.