| 摘要 |
A PLD includes buffered interconnect resources and configurable logic circuits that are controlled by data stored in a configuration memory. Each buffer of the buffered interconnect resources includes a feedback pull-up transistor. To avoid crowbar current problems, a high voltage is transmitted to the input terminals of all buffers before configuration, thereby biasing all buffers into a high feedback voltage mode. In one embodiment, the high voltage is transmitted to the buffers using a global control signal that forces all output drivers to generate high output voltages, and then turning on all pass transistors of the interconnect resources to broadcast the high voltages to every buffer. After configuration, the global control signal is de-activated. In another embodiment, each buffer circuit includes a second pull-up device that is turned on at power-up to force all buffers into the high feedback mode. In this embodiment, all pass transistors of the interconnect resources are turned off before configuration. In yet another embodiment, another global control signal is transmitted to all state devices of the PLD at the beginning of a stand-by/reconfiguration mode. In response to the additional control signal, all state devices ignore subsequent signals from the interconnect resources until configuration is completed and all output drivers are returned to their pre-stand-by operation state.
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