| 摘要 |
An apparatus for conducting serial bus transactions. The embodiments of the invention permit a reduction in the die space allocated to buffering in chipsets supporting a high speed serial bus. Buffering currently occupies a substantial proportion of total die area. That proportion is expected to increase as the serial protocols implemented gain speed. Accordingly, control of buffers sizes is expected to provide a significant cost benefit both now and in the future. In one embodiment, a transceiver is provided. A plurality of FIFOs are allocatable from a shared buffer pool, each FIFO corresponding to a serial bus transaction type. A plurality of direct memory access controllers (DMAs) are coupled to the FIFO and fill or empty the FIFO. A link layer provides an interface between the transceiver and the FIFOs permitting the transceiver to conduct transactions to and from the FIFOs. In another embodiment of the invention, again a transceiver is provided. A FIFO smaller than a default packet size of an associated transaction type is employed. A link layer provides an interface between the small FIFO and the transceiver. The link layer also sets a control register to dictate packet size so that an upstream system can handle transfers of the packet size eventhough constrained by the small FIFO.
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