| 摘要 |
A semiconductor integrated circuit for shortening totally access time in controlling accesses (read/write) from a plurality of access request sources (masters) to a memory block including a plurality of memory banks. By exploiting the properties of the masters, a memory control circuit for changing the contents of the memory access control is employed for each master. Specifically, when a first master having a property of accessing repeatedly the same page (word line) in the same memory bank makes an access request, this memory control circuit ends the access, with the page opened by the access open (bank active). On the contrary, when a second master having a low probability of repeated access to the same page makes an access request, the circuit closes the page opened by the access and ends the (pre-charge) access. This access control is useful especially for saving time to bring a DRAM word line (one word page) into a selected or nonselected state. |
