发明名称
摘要 <p>PROBLEM TO BE SOLVED: To suppress the increase in processing load in CFAR detecting processing (erroneous alarm ratio constant) even when the number of Doppler filters is increased in order to improve a target detecting performance in a radar signal processing device. SOLUTION: A radar loaded airplane frequency calculating circuit 5 calculates radar loaded airplane frequency, a comparing circuit 6 generates a L-level integration control signal when the corresponding frequency of a received data to be processed in data integration is the radar loaded airplane frequency or lower, and generates an H-level integrated control signal when it is larger. A data integrating circuit 7 substitutes (j)-pieces of received data from an amplitude calculating circuit 2 by the maximum data therein according to the H-level integrated control signal-, and supplies them to the corresponding memory cells of a memory circuit 3, and the data is outputted without integration as it is in case of the L-level integration control signal. A CFAR detecting circuit 4 successively performs the CFAR detecting processing of the integrated or non-integrated amplitude value data which is stored in each memory cell as noticed data, whereby a target is precisely detected while reducing the increase in processing load in the CFAR detecting processing.</p>
申请公布号 JP3199652(B2) 申请公布日期 2001.08.20
申请号 JP19960344923 申请日期 1996.12.25
申请人 发明人
分类号 G01S7/32;G01S13/53;(IPC1-7):G01S7/32 主分类号 G01S7/32
代理机构 代理人
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