WIRING STRUCTURE OF INTEGRATED CIRCUIT AND MANUFACTURING METHOD THEREOF

摘要

PURPOSE: A wiring structure of integrated circuit and manufacturing method thereof is provided to reduce a contact resistance between a word line and a bit line in spite of the large resistance of a depletion layer by contacting the bit line with all silicon film pattern and silicide film pattern forming the word line. CONSTITUTION: A gate oxide film(101) is formed on a semiconductor substrate(100). The first silicon film pattern having a predetermined width is formed on the gate oxide film(101). The first silicide film pattern having a width narrower than the first silicon film pattern is formed on the first silicon film pattern to expose a portion of the first silicon film pattern. A word line(150) comprises the first silicide film pattern. A bit line(160) is formed to contact the exposed portion of the first silicon film pattern.