CIRCUIT FOR CONTROLLING LATENCY OF SEMICONDUCTOR DEVICE USING DELAY LOCKED LOOP

摘要

PURPOSE: A circuit for controlling latency of a semiconductor device is to exactly output data according to the latency using a DLL(delay locked loop) clock signal locked with the first and second edge of an outer clock signal. CONSTITUTION: A delaying portion(100) inputs a signal for informing a starting time and an ending time to delay output of data, when reading the data at an outside. The delaying portion outputs the delayed signal as a starting/ending signal. A DDL(130) delays an outer clock signal for a desired time and generates the first and second delay clock signal locked with the first and second edge of the outer clock signal. A latency controlling portion(120) delays the starting/ending signal responding to the first and second delaying clock signal output from the DDL. An output control portion(140) generates an output buffer control signal for outputting the data responding to the first and second delay clock signal and the latency signal generated from the latency controlling portion.