| 摘要 |
PURPOSE: A circuit for generating local output clock signal at proper time is provided to attain an optimum signal generating time by avoiding a defect caused by a propagation time in a circuit generating a local output clock signal to control a point of time, at which data is sent out from a sending out delay mechanism in an output side of a memory field to a data path. CONSTITUTION: In a DDR-SDRAM memory chip, a highly accurate output clock signal is required for sending stored data to a data path at an appropriate point of time, such an output clock signal is generated by a symmetric circuit(1). This circuit generates an output clock signal in the minimum time by integrating a multiplexer to a pulse ratio compensating circuit consisting of two branches(2, 3) being symmetric to each other.
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