发明名称
摘要 <p>PROBLEM TO BE SOLVED: To shorten a reading time by providing two pairs of latch circuit group holding data read out from a memory cell and operating them for reading data and outputting data alter-nately. SOLUTION: When an EEPROM of power source voltage 3V is made four values system, threshold values of 0.5-0.8V, 1.5-1.8V, 2.5-2.8V are allotted to data '1', '2', '3' of negative threshold values for data '0'. At the time of read-out, a data circuit 6** tests continuity of a memory cell by applying three kinds of voltage values 1V, 2V, 0V in this order as read-out voltage, and discriminates stored data '0', '1', '2', '3'. Then, the result of sense by read-out voltage is held by using alternately a first and a second latch circuit group RT1**, RT2**, for example, the result is outputted to the outside from the other latch circuit group RT2** while the result is read in one side of latch circuit group RT1**.</p>
申请公布号 JP3200006(B2) 申请公布日期 2001.08.20
申请号 JP19960061445 申请日期 1996.03.18
申请人 发明人
分类号 G11C17/00;G11C16/02;G11C16/04;(IPC1-7):G11C16/02 主分类号 G11C17/00
代理机构 代理人
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