发明名称 METHOD FOR DESIGNING AND VERIFYING LSI
摘要 PROBLEM TO BE SOLVED: To improve the secrecy of circuit design data more than conventional by adopting enciphering processing to the design of an LSI. SOLUTION: In enciphering processing SA, design data 11 of a circuit requiring secrecy are enciphered and enciphered design data 12 and a key 13 for deciphering are generated. A dummy circuit is located parallel with an original circuit and a selector is located for selecting signals as many as the outputs of the original circuit out of outputs relocating the outputs of that dummy circuit. The select signal of the selector becomes a key. The enciphered design data 12 are provided to a user to execute designing/verifying processing S2 and the key 13 is provided together as needed. In designing/verifying processing SB, concerning the enciphered design data 12, various kinds of processing are performed while keeping the secret of contents of the original circuit. In deciphering processing SC, enciphered design data 14 after the execution of designing/verifying processing SB are deciphered and original circuit design data 16 are generated.
申请公布号 JP2001222571(A) 申请公布日期 2001.08.17
申请号 JP20000034577 申请日期 2000.02.14
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 SHIOMI KENTARO;MOTOHARA AKIRA;FUJIWARA MUTSUMI;YOKOYAMA TOSHIYUKI;FUJIMURA KATSUYA
分类号 G01R31/28;G06F12/14;G06F17/50;G06F21/00;G06F21/24;G09C1/00;H01L21/82;H01L29/00 主分类号 G01R31/28
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