| 摘要 |
PROBLEM TO BE SOLVED: To speed up conversion into a physical address and the judgment of a cache hit. SOLUTION: A DTLB in a microprocessor of this invention is provided with an adder for adding a base address and a code-extended offset address, a comparator for judging whether the upper twenty bits [31:12] of the base address coincide with the base address stored in an upper address storing part in a CAM 35 and whether the upper four bits of an offset address coincide with an offset address stored in the CAM 35 or not, a comparator for judging whether a carry signal outputted from the adder coincides with a carry signal stored in a carry storing part in the CAM 35, and a coincidence detection part for outputting a coincidence signal when the comparison results of both the comparators coincide. Since the coincidence/-non-coincidence of the lower twelve bits of a virtual address is judged only by a carry signal, the coincidence/non- coincidence of the virtual address can be judged before completing the addition processing of the adder.
|
