发明名称 |
TESTING APPARATUS AND METHOD |
摘要 |
PROBLEM TO BE SOLVED: To attain a higher trouble coverage with a shorter test length by reducing the number of necessary hardwares. SOLUTION: Original test vectors stored in an ROM 4 are shifted alternately into two shift registers SR-A2 and SR-B3 on a vector basis. The vectors in the shift registers SR-A2 and SR-B3 are shifted into multiplexers MUX5-1, 5-2 and 5-3 alternately together with pseudo random vectors generated by an LFSR1, to be mutually multiplexed. The multiplexed vectors are mixed vectors, and are printed to a CUT6 separately from the multiplexers MUX5-1, 5-2 and 5-m.
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申请公布号 |
JP2001221836(A) |
申请公布日期 |
2001.08.17 |
申请号 |
JP20000028823 |
申请日期 |
2000.02.07 |
申请人 |
JAPAN SCIENCE & TECHNOLOGY CORP |
发明人 |
IWASAKI KAZUHIKO;ASAKAWA TAKESHI |
分类号 |
G01R31/3183;G01R31/28;(IPC1-7):G01R31/318 |
主分类号 |
G01R31/3183 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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