| 摘要 |
PROBLEM TO BE SOLVED: To provide a wafer and a wafer test system which accomplish testing, without impairing the integration level of LSIs and the number of pins at a lower cost in a wafer on which dies are formed. SOLUTION: In a wafer test system of a wafer 1 on which a plurality of dies 4 are formed, a wafer 1 has a test pattern supply circuit 3 for supplying a test pattern to each of the plurality of dies 4 and a comparator circuit 5, which inputs a plurality of results of testing outputted separately from the plurality of dies 4 in response to the respective test patterns supplied from the test pattern supply circuit 3 to compare the plurality of results inputted and judges the propriety of the results compared to output the judged results. The testing of the wafer is implemented using the wafer 1.
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