发明名称 MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE
摘要 PROBLEM TO BE SOLVED: To improve gate breakdown voltage and reliability by relaxing concentration of electric field at a step part formed near a boundary between an active region and a field region trench, and suppressing production of a parasitic MOS in manufacture of a trench element isolation. SOLUTION: This manufacturing method contains a process wherein an antioxidizing film pattern 13 is formed on an active region of a substrate 11, a process wherein an element isolation region of the substrate 11 is oxidized selectively to form an oxide film 14 that gets under the peripheral part of the anti-oxidizing film pattern 13, a process wherein the oxide film 14 that is not covered with the anti-oxidizing film pattern 13 is removed with the anti- oxidizing film pattern 13 as a mask, a process wherein a trench 15 is formed in the substrate 11 with the anti-oxidizing film pattern 13 as a mask, a process wherein an insulation film 16 with which the trench 15 is filled is formed on the substrate 11, a process wherein the insulation film 16 other than that in the trench 15 is removed, and a process wherein the antioxidizing film pattern 13 is removed.
申请公布号 JP2001223264(A) 申请公布日期 2001.08.17
申请号 JP20000031520 申请日期 2000.02.09
申请人 SONY CORP 发明人 KOMATSU YUJI
分类号 H01L21/76;H01L21/762;H01L29/78;H01L29/786;(IPC1-7):H01L21/76 主分类号 H01L21/76
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