发明名称 |
Testing semiconducting wafers involves electrically testing each chip on each wafer to identify sub-area with most wafers with more defective chips in sub-area than in surrounding area |
摘要 |
The method involves dividing each wafer into areas and sub-areas, electrically testing each chip on each wafer, determining the fraction of chips per sub-area failing the test, determining the number of wafers per sub-area with a higher proportion of failing chips than in the surrounding area and outputting the sub-area with most wafers in which the proportion of defective chips in the sub-area is greater than in the surrounding area.
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申请公布号 |
DE10036961(A1) |
申请公布日期 |
2001.08.16 |
申请号 |
DE20001036961 |
申请日期 |
2000.07.28 |
申请人 |
PROMOS TECHNOLOGIES, INC.;MOSEL VITELIC INC., HSINCHU;INFINEON TECHNOLOGIES AG |
发明人 |
CHIOU, CINDY |
分类号 |
H01L21/66;(IPC1-7):H01L21/66 |
主分类号 |
H01L21/66 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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