| 摘要 |
A data processing device having a DMA function for controlling DMA transfer, comprises a DMA unit (10), a CPU (20), a bus arbitration unit (30) for controlling bus-using right of the DMA unit (10) or the CPU (20), and an interruption controller (40) for supplying an interruption request signal, the data processing device in which the DMA unit (10) includes a register (11) and a comparator (12) for making a comparison between the priority set on the DMA unit (10) and the priority set on the interruption request, and a sequencer (18) for deciding the DMA transfer to be executed, canceled, or suspended in the operation state of the DMA unit (10) according to the comparison result of the comparator (12). <IMAGE> |
