| 摘要 |
PURPOSE: A method for fabricating a capacitor is provided, which has a MIM(Metal-Insulator-Metal) structure to have a symmetric C-V curve, and to increase an effective surface area of a bottom electrode of the capacitor without using a process of forming an HSG(Hemispherical Silicon Grain) film. CONSTITUTION: A gate oxide and a gate electrode(221) are formed on a semiconductor substrate(200), and a source(222) and a drain(223) are formed by implanting an impurity into the substrate on both sides of the gate electrode to form a MOS transistor(220). An interlayer insulation film(202) is formed with a silicon oxide on the substrate, and then a contact hole(203) is formed on the location of the source by etching the interlayer insulation film. A conductive plug(204) is formed in the contact hole, and a metal film pattern(205) is formed on the polysilicon plug and the interlayer insulation film. Then a polysilicon layer(206) is formed on the metal film pattern and the interlayer insulation film. And a silicidation reaction occurs by thermally treating the polysilicon layer and the metal film pattern to form a silicide layer(207). And the residual polysilicon layer is selectively etched. The silicide layer surrounding the surface of the metal film pattern is removed. After forming a dielectric film(208) on the surface of the metal film pattern, a top electrode(209) of the capacitor is formed on the surface of the dielectric film.
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