| 摘要 |
In a level shifter including a latch consisting of two p-channel transistors P1 and P2, when an input signal at a terminal IN changes from H- into L-level, an n-channel transistor N2 turns ON, thereby dropping a potential level at a node W2. However, since a p-channel transistor P4 is OFF, no short-circuit current flows from a high voltage supply VDD3 into the ground by way of the transistors P2 and N2. On the other hand, since n- and p-channel transistors N1 and P3 are OFF, both terminals of a node W1 are electrically isolated. But the high voltage supply VDD3 pulls the node W1 up to a high voltage level by way of the p-channel transistors P4 and P1 and another p-channel transistor P5 as a resistor. Accordingly, the capacitance to be driven by the n-channel transistors N1 and N2 can be reduced, thus shortening the delay.
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