发明名称 Methods and systems for performing short integer chen IDCT algorithm with fused multiply/add
摘要 Methods and apparatus for performing a fast two-dimensional inverse discrete cosine transform (IDCT) in a media processor are disclosed. A processor receives at least one input component representing discrete cosine transform data and combines, in a first stage, the at least one input component with a first set of constants. In a media processor with a partitioned SIMD architecture, the input data and first set of constants may be combined, for example, by multiplying the at least one input component with a first set of constants using a complex multiplication instruction. The output is transposed in a second stage and combined with constants in a third stage.
申请公布号 US2001014904(A1) 申请公布日期 2001.08.16
申请号 US20010828231 申请日期 2001.04.09
申请人 SONY ELECTRONICS, INC. 发明人 WANG NAXIN
分类号 G06F17/14;(IPC1-7):G06F17/14 主分类号 G06F17/14
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