| 摘要 |
A number of control signals are provided, where each is responsive to a phase error measured at a different time between a first oscillatory signal and a number of second oscillatory signals. A node is either charged or discharged using a number of charged storage devices, where each device has a predetermined capacitance, in response to the number of first control signals. The method is applicable in frequency control circuit applications such as phase locked loops (PLLs), delay locked loops (DLLs) and clock recovery circuits (CRCs).
|
