Error detection and correction interleave system

摘要

An error detection and correction interleave system (18) has M memory devices (20) for storing electronic data and a controller (22) to insure data integrity. Each memory device (20) has a plurality of memory addresses (28) corresponding to a plurality of N bit words (26). Each N bit word (26) in each memory device (20) has a unique memory address (28). A controller (22) is coupled to the M memory devices (20) and collects one bit from each N bit word (26) from each memory device (20) for each memory address (28). This generates a total of N EDAC groupings (30), each having a length of M bits. The controller then generates N error detection and correction codes for each EDAC grouping (30) (Fig. 2). <IMAGE>