| 摘要 |
<p>A system and a method for selectively placing a computer memory device (100), even when its data/address pins (104) are multiplexed, into a special test mode. In order to allow the manufacturer of a memory device to selectively enter into one of a plurality of special high-speed tests, while preventing an ordinary user of the memory device from accidentally entering into such test modes, a combination of one or more high voltage pins and a sequence of test-mode commands (303, 304) are used to selectively enter into a special test mode. The high voltage pin serves as an enable signal input to a test-mode command decoder (202) to enable it for receiving and recognizing a specific sequence of test-mode commands (303, 304). The specific sequence of test-mode commands (303, 304) is supplied to selectively put the memory device in one of a plurality of test modes.</p> |
