发明名称 An integrated circuit and a method of manufacturing an integrtaed circuit
摘要 An apparatus and process to assess the occurrence or the likelihood of a failure in an integrated circuit. The process includes forming a conductive region such as a runner about the periphery of a substrate or die. The conductive regions may be located at one of more different metallization layers within the integrated circuit. The conductive region is couple to one or more of the bond pads. The die is assessed by measuring the resistance, conductivity, cross talk or other electrical characteristics on the conductive region via the bond pads. The assessment can then be used to predict whether, for example, the runners formed in the integrated circuit have failed or are likely to fail.
申请公布号 GB0115078(D0) 申请公布日期 2001.08.15
申请号 GB20010015078 申请日期 2001.06.20
申请人 AGERE SYSTEMS GUARDIAN CORPORATION 发明人
分类号 G01R31/28;H01L21/3205;H01L21/60;H01L21/822;H01L23/52;H01L23/544;H01L27/04 主分类号 G01R31/28
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